The increasing demand for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as adder. Adder plays an important role in arithmetic operation such as addition, subtraction, multiplication, division etc. The characterization and optimization of such low power adder will aid in comparison and choice of adder modules in system design. In this paper we performed a comparative analysis of the power, delay, and power delay product (PDP) optimization characteristic.. This paper deals with the design of some adder using transistors and simulations is done with DSCH 3.1 and Microwind3.1 CAD tool. 10 transistor adder circuit shows the least power consumption among others.
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